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E2C0010-27-Y4
Semiconductor MSC1163
Semiconductor 40-Bit Anode Driver
This version: Nov. 1997 MSC1163 Previous version: Jul. 1996
GENERAL DESCRIPTION
The MSC1163 is a monolithic IC using the Bi-CMOS process for hybridizing CMOS and bipolar transistors on the same chip. The logic portion such as the input stage, shift register and latch is fabricated by CMOS and the output driver requiring a high withstand voltage is fabricated by bipolar transistors. Since the 60-pin plastic SSOP package is adopted and the pin configuration allows the circuit wiring to be formed on the single side PCB, the display unit size can be reduced. The shift register has a bidirectional configuration; therefore, it is easy to design the circuit wiring in which devices are arranged so that they are symmetric with respect to the display.
FEATURES
The MSC1163 is designed as a VFD anode driver with emitter-follower output providing 40-bit active pull-down and built-in 40-bit bidirectional shift register and latch. * Logic Supply Voltage (VCC) : 5V * Driver Supply Voltage (VHV) : 65V * Driver Output Current IOHVH : -2mA IOHVL : 2mA * Built-in 40-bit output with latch * Built-in 40-bit bidirectional shift register * Clock frequency: 4MHz * Package: 60-pin plastic SSOP (SSOP60-P-700-0.65-BK)
(Product name: MSC1163GS-BK)
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MSC1163
BLOCK DIAGRAM
V CC V CC V HV V HV (1 to 20)(21 to 40)(1 to 20)(21 to 40)
CLK
DIN R/L
LS
CHG
CL
D HVO1 R-1 1 1 HVO2 R-2 2 2
40-Bit Bi-directional Shift Register
40-Bit Latch
HVO40 40 40 Q
R-40
DOUT
(1 to 20)(21 to 40)
GND2 GND2
(1 to 20) (21 to 40)
GND1 GND1
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MSC1163
INPUT AND OUTPUT CONFIGURATION
Schematic Diagrams of Logic Portion Input and Output Circuits Input pin
VCC VCC
INPUT
GND1
GND2
Output pin
VCC
VCC
DOUT
GND2
GND1
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Semiconductor Schematic Diagram of Driver Output Circuit
MSC1163
VHV
VHV
HVO
GND 1
GND 1
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Semiconductor
PIN CONFIGURATION (TOP VIEW)

HVO 1 HVO 2 HVO 3 HVO 4 HVO 5 HVO 6 HVO 7 HVO 8 HVO 9 HVO 10 HVO 11 HVO 12 HVO 13 HVO 14 HVO 15 HVO 16 HVO 17 HVO 18 HVO 19 HVO 20 VHV GND 1 GND 2 CL NC LS NC R/L DIN VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC : No-connection pin 60-Pin Plastic SSOP
MSC1163
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
HVO 40 HVO 39 HVO 38 HVO 37 HVO 36 HVO 35 HVO 34 HVO 33 HVO 32 HVO 31 HVO 30 HVO 29 HVO 28 HVO 27 HVO 26 HVO 25 HVO 24 HVO 23 HVO 22 HVO 21 VHV GND 1 GND 2 NC CHG NC CLK NC DOUT VCC
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MSC1163
PIN DESCRIPTION
Function Driver Output Driver Power Supply Driver GND Pin 1 - 20 41 - 60 21 40 22 39 23 38 24 Symbol HVO1 HVO40 VHV GND 1 Type O -- -- Description Driver output pin, applicable to each bit of shift register Power supply pin for driver circuit GND pin for driver circuit. Connect this pin to GND2 near the mounted IC so that GND1 and GND2 will be at common level. GND pin for the logic circuit (excluding driver circuit) GND1 and GND2 are not connected inside of the IC. Clear input pin with pull-up resistor. Normally "H" level. In this condition, the driver outputs "H" or "L" according to the corresponding latch output level. Setting to "L" enables the driver output to be fixed at "L" without respect to latch output. Latch strobe input pin with neither pull-up nor pull-down resistor. When LS is "H", the output of the shift register becomes that of the latch circuit. When LS is "L", the latch circuit holds the contents of the shift register before LS goes "L". Shift direction control pin with a pull-up resistor. Normally "H", and in this condition, data of bidirectional shift register is shifted to the direction of R-40 from R-1. When this pin is "L", bidirectional shift register shifts data to the direction of R-1 from R-40. Shift register input pin with neither pull-up nor pull-down resistor. Display data is input in synchronization with clock. (Positive logic) Power supply pin for logic (except driver) VCC should be 4.5V to 5.5V. Serial output of bidirectional pin shift register. When R/L is "H", DOUT outputs R-40's output. When R/L is "L", DOUT outputs R-1's output. Clock input pin with neither pull-up nor pull-down resistor. Data of shift register is shifted from one stage to the next at the rising edge of clock. Test input pin with a pull-down resistor. Normally "L". If CL = "H" in this condition, the driver outputs "H" or "L" according to the corresponding latch output. If CL = "H", setting CHG to "H" enables the driver output to be fixed at "H" without respect to latch output.
Logic GND Clear Input
GND 2 CL
-- I
Latch Strobe Input
26
LS
I
Shift Direction Control
28
R/L
I
Data Input
29
DIN
I
Logic Power Supply Data Output
30 31 32
VCC DOUT
-- O
Clock Input
34
CLK
I
Test Input
36
CHG
I
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Semiconductor
MSC1163
ABSOLUTE MAXIMUM RATINGS
Parameter Logic Supply Voltage Driver Supply Voltage Input Voltage Data Output Voltage Driver Driving Frequency Power Dissipation Package Thermal Resistance Storage Temperature Symbol VCC VHV VIN VOD fDRV PD Rj-a TSTG Condition Applicable to logic supply voltage pin Applicable to driver supply voltage pin Applicable to all input pins Applicable to data output pin Duty cycle 50% max Ta 25C -- -- Rating -0.3 to +6.5 VCC to 70 -0.3 to VCC +0.3 -0.3 to VCC +0.3 0 to 15 860 145 -55 to +150 Unit V V V V kHz mW C/W C Note 1 1, 2 1 1 -- -- 3 --
Notes: 1) Maximum Supply Voltage with respect to GND 2) Permanent damage may be caused if the voltage is supplied over the rating. 3) Package Thermal Resistance (between junction and atmosphere) The junction temperature (Tj) given by the equation indicated below should not exceed 150C. Tj=P Rj-a+Ta (P: Maximum power consumption)
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MSC1163
RECOMMENDED OPERATING CONDITIONS
Parameter Logic Supply Voltage Driver Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Driver Output Current Low Level Driver Output Current CLK Frequency CLK Pulse Width Data in Setup Time Data in Hold Time LS Pulse Width CLK-LS Delay Time LS-CLK Delay Time LS-CHG Delay Time LS-CL Delay Time CHG Pulse Width CL Pulse Width Operating Temperature Symbol VCC VHV VIH VIL IOHVH IOHVL ff tWCLK tDS tDH tWLS tDCL tDLC tDLCG tDLCL tWCHG tWCL Top Condition Applicable to logic supply voltage pin Applicable to driver supply voltage pin Applicable to all input pins Applicable to all input pins VCC=4.5V VCC=5.5V VCC=4.5V VCC=5.5V Min. 4.5 10 3.6 4.4 -- -- -- -- -- 75 50 50 80 50 0 0 0 2 2 -40 Max. 5.5 65 -- -- 0.9 1.1 -2 2 4 -- -- -- -- -- -- -- -- -- -- 85 Unit V V V V V V mA mA MHz ns ns ns ns ns ns ms ms ms ms C
Applicable to all driver output pins Applicable to all driver output pins See timing diagram See timing diagram See timing diagram See timing diagram See timing diagram See timing diagram See timing diagram See timing diagram See timing diagram See timing diagram See timing diagram --
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MSC1163
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VCC=5V10%, VHV=10V to 65V, Ta=-40C to +85C) Parameter Logic Supply Current Symbol ICC1 ICC2 IHV1 Driver Supply Current IHV2 VIH VIL IIN CIN VODH1 VODL1 VODH2 VODL2 VOHVH VOHVL IO=-20mA IO=20mA IO=-0.1mA IO=0.1mA No load VCC=5.5V No load VCC=5.5V -- -- Condition All input: Low All input: High, All driver output: High, Ta=25C All driver output: Low All driver output: High, Ta=25C VCC=4.5V VCC=5.5V VCC=4.5V VCC=5.5V Ta=25C Ta=25C VCC=4.5V VCC=5.5V VCC=4.5V VCC=5.5V VCC=4.5V VCC=5.5V VCC=4.5V VCC=5.5V IOHV=-2mA IOHV=2mA Min. -- -- -- -- 3.15 3.85 -- -- -- -- 4.2 5.2 -- -- 3.5 4.5 -- -- VHV-3 -- Typ. 4.3 0.5 -- 2.45 -- -- -- -- -- 15 -- -- -- -- -- -- -- -- -- -- Max. 6.65 1.0 1 3.8 -- -- 1.35 1.65 1 -- -- -- 0.2 0.2 -- -- 1.1 1.1 -- 3.0 mA mA mA V V V V mA pF V V V V V V V V V V Unit
High Level Input Voltage Low Level Input Voltage Input Leakage Current Input Capacitance High Level Data Output Voltage Low Level Data Output Voltage High Level Data Output Voltage Low Level Data Output Voltage High Level Driver Output Voltage Low Level Driver Output Voltage
AC Characteristics
(VCC=5V, VHV=65V, Ta=25C) Parameter CLK-DOUT Delay Time Delay Time Low to High Transit Time Low to High Delay Time High to Low Transit Time High to Low Symbol tPD tDLH tTLH tDHL tTHL Condition See timing diagram and test circuit See timing diagram and test circuit See timing diagram and test circuit See timing diagram and test circuit See timing diagram and test circuit Min. -- -- -- -- -- Typ. 100 0.3 3 0.3 2 Max. 150 1 5 1 5 Unit ns ms ms ms ms
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Semiconductor
TIMING DIAGRAM
1/f f CLOCK T1/2 tDS tDH DIN tWD DOUT tDCL tWLS LS tDLCG CHG tWCHG tDLCL CL tDLH HVO (1, 2, 39, 40) tDLH tDHL tDHL 90% 10% 90% 10% tTLH tTLH tTHL tTHL tTLH tDLH tWCHG tWCL tWCL tDLC tPD tPD T3/4 T39/40 tDS tDH T1/2 tWCLK tWCLK T3/4
HVO (OTHERS)
MSC1163
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Semiconductor Test circuit
MSC1163
20pF V CC V HV HVO1 30kW HVO2
65V
5.0V HVO40
GND1, 2
CHG
CLK
R/L
DIN
DOUT
LS
CL
30pF
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MSC1163
FUNCTIONAL DESCRIPTION
Notes on Use 1. The MSC1163GS is designed as an anode driver of VFD. The data applied to the data input pin is read into the shift register at the rising edge of the clock and shifted sequencially to the shift register synchronizing with the clock. The shift register output drives the output driver, passing through the latch and the NOR circuit. Setting the CL pin to "L" makes all driver outputs go into "L". This function can be used for setting display blanking. 2. The contents of the shift register are undefined after power is turned on. Therefore, two or more driver outputs may go into "H" at the same time after poweron. To avoid this, take the following procedure: 1) Turn on the power of the logic portion while holding the CL pin to "L". 2) Turn on the power of the driver portion. 3) Apply a "L" level signal to the DIN pin and send clock pulses by the specified number of grids to reset ("L") the entire contents of the shift register.
Function Table
CLK R/L H H L L CL L H H H H CHG X H L L L DIN H L H L LS X X H H L R-1 H L R2n R2n R-2 R1n R1n R3n R3n R.X X X H L X R-3 R2n R2n R4n R4n HVO.X L H H L NC R-4 R3n R3n R5n R5n ******** R-40 R39n R39n H L DOUT R39n R39n R2n R2n
L : Low Level, H: High Level, X: Don't Care, NC: No Change
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MSC1163
PACKAGE DIMENSIONS
(Unit : mm)
SSOP60-P-700-0.65-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.21 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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